{"id":1354,"date":"2026-04-14T13:37:01","date_gmt":"2026-04-14T17:37:01","guid":{"rendered":"https:\/\/carleton.ca\/doe-4th-projects\/?post_type=cu-people&p=1354"},"modified":"2026-04-20T10:41:07","modified_gmt":"2026-04-20T14:41:07","slug":"rony-amaya","status":"publish","type":"cu-people","link":"https:\/\/carleton.ca\/doe-4th-projects\/people\/rony-amaya\/","title":{"rendered":"Rony Amaya"},"content":{"rendered":"

Project Area<\/strong>: High-Speed Electronics \/ Wireline Communications \/ Advanced Packaging<\/p>\n

Project Title<\/strong>: LPO inspired High-Speed Electronics and Advanced Packaging for 400Gbps and beyond<\/p>\n

\"\"<\/p>\n

Project Description<\/strong>: This Ciena-inspired project promises to deliver Linear Pluggable Optic (LPO) systems capable of ultra-fast Gbps transmission and with low energy efficiency. LPOs reduce the need for DSP retimers, thereby lowering power consumption [1].<\/p>\n

The project is structured into three key sub-groups:<\/p>\n

    \n
  1. Subgroup 1: System Analysis of LPOs. This will be carried out in MATLAB, Simulink or ADS and will define the technical specs for subgroups 2 and 3. Ideally, support 2 to 3 students.<\/li>\n
  2. Subgroup 2: IC design. Key IC blocks in LPOs will be addressed here. Typical circuits include Driver and Continuous-Time Linear Equalizers (CTLE), Linear Transimpedance Amplifier (TIA), and SERDES analog equalizers. There will be strong interaction with subgroups 1 and 3. Ideally, support 3 to 4 students.<\/li>\n
  3. Subgroup 3: Advanced Packaging. LPO interface to understand the propagation channel. Evaluation of commercial packaging substrates and interconnects, bondwires vs flip-chip BGAs. Metamaterials to control propagation in the substrates explored here. Strong interaction with IC design and drawing specs from the System subgroup. Ideally, support 2 to 3 students.<\/li>\n<\/ol>\n

    This project will be of interest to students with a strong background in ELEC 3509 and ELEC 3909, who will register for ELEC 4609 and ELEC 4706 in Fall 2026. This project is inspired by Ciena and offers strong opportunities for internship and\/or graduate studies after project completion. If you are serious about this project, I strongly encourage you to read the reference below [1].<\/p>\n

    Reference:
    \n[1] https:\/\/eps.ieee.org\/wp-content\/uploads\/2026\/03\/Linear-Pluggable-Optics_V2-UPDATED.pdf<\/p>\n

    Tentative Sub-Titles<\/strong>:<\/p>\n

      \n
    • System Analysis Group – Linear Pluggable Optics (LPO) to reduce need for re-timers and improve system efficiency below 5pJ\/bit. Define the specs for the IC and Packaging groups.<\/li>\n
    • Integrated Circuit (IC) Design Group – Electronics Interface to LPO. This will include TIA, analog equalizers, Continuous Time Linear Equalizers (CTLE), Drivers. Strong interaction with the Packaging group.<\/li>\n
    • Advance Packaging Group – Define the interface of LPO to reduce the need for DSP retimers. Explore packaging technology options, interconnects bondwires vs flip-chip BGA bonding. Metamaterials for engineer propagation into packaging substrates.<\/li>\n<\/ul>\n

      Desired Technical Skills<\/strong><\/p>\n

      IC circuit design (ELC3509), EM (ELEC 3909), Strongly suggest to take ELEC 4609 and ELEC 4706 in Fall 2026.<\/p>\n","protected":false},"template":"","meta":{"_relevanssi_hide_post":"","_relevanssi_hide_content":"","_relevanssi_pin_for_all":"","_relevanssi_pin_keywords":"","_relevanssi_unpin_keywords":"","_relevanssi_related_keywords":"","_relevanssi_related_include_ids":"","_relevanssi_related_exclude_ids":"","_relevanssi_related_no_append":"","_relevanssi_related_not_related":"","_relevanssi_related_posts":"","_relevanssi_noindex_reason":"","_mi_skip_tracking":false,"_exactmetrics_sitenote_active":false,"_exactmetrics_sitenote_note":"","_exactmetrics_sitenote_category":0,"_monsterinsights_sitenote_active":false,"_monsterinsights_sitenote_note":"","_monsterinsights_sitenote_category":0,"_links_to":"","_links_to_target":""},"people-type":[34],"yoast_head":"\nRony Amaya - Department of Electronics 4th-Year Engineering Project<\/title>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"https:\/\/carleton.ca\/doe-4th-projects\/people\/rony-amaya\/\" \/>\n<meta name=\"twitter:label1\" content=\"Est. reading time\" \/>\n\t<meta name=\"twitter:data1\" content=\"2 minutes\" \/>\n<script type=\"application\/ld+json\" class=\"yoast-schema-graph\">{\"@context\":\"https:\/\/schema.org\",\"@graph\":[{\"@type\":\"WebPage\",\"@id\":\"https:\/\/carleton.ca\/doe-4th-projects\/people\/rony-amaya\/\",\"url\":\"https:\/\/carleton.ca\/doe-4th-projects\/people\/rony-amaya\/\",\"name\":\"Rony Amaya - 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