{"id":15008,"date":"2022-06-16T19:47:34","date_gmt":"2022-06-16T23:47:34","guid":{"rendered":"https:\/\/carleton.ca\/scs\/?page_id=15008"},"modified":"2022-06-16T19:47:34","modified_gmt":"2022-06-16T23:47:34","slug":"tr-198-on-reconfigurability-of-systolic-arrays","status":"publish","type":"page","link":"https:\/\/carleton.ca\/scs\/research\/scs-technical-reports\/technical-reports-1991\/tr-198-on-reconfigurability-of-systolic-arrays\/","title":{"rendered":"TR-198: On Reconfigurability of Systolic Arrays"},"content":{"rendered":"

Carleton University
\nTechnical Report<\/a> TR-198<\/strong>
\nNovember 1991<\/p>\n

On Reconfigurability of Systolic Arrays<\/h2>\n
Amiya Nayak, Nicola Santoro, Richard Tan<\/div>\n
\n

Abstract<\/h3>\n

This paper deals with identification, characterization, and catastrophic fault patterns that are catastrophic for systolic arrays. It is shown that for a given link configuration in the array, it is possible to identify all PE (processing element) catastrophic fault patterns. The requirement on the minimum number of faults in a fault pattern and its spectrum (spread out) for it to be catastrophic is shown to be function of the length of the longest bypass link available, and not of the total number of bypass links. This paper also discusses the effect of PE failures on computation performed on one-dimensional VLSI processor arrays. All the established properties of catastrophic fault patterns are used to study inherent limits to reconfigurability of these regular architectures. Bounds on number of faults the system can tolerate to provide guaranteed performance are derived.<\/p>\n<\/div>\n

TR-198.pdf<\/a><\/p>\n