{"id":348,"date":"2026-04-30T11:07:42","date_gmt":"2026-04-30T15:07:42","guid":{"rendered":"https:\/\/carleton.ca\/share\/?p=348"},"modified":"2026-04-30T11:07:42","modified_gmt":"2026-04-30T15:07:42","slug":"new-publication-4","status":"publish","type":"post","link":"https:\/\/carleton.ca\/share\/2026\/new-publication-4\/","title":{"rendered":"New Publication"},"content":{"rendered":"

Aaron Yu; Arash Ahmadi; Leonard MacEachern, “A Spiking Neural Network Based Hough Transform Implementation for FPGAs”, IEEE Transactions on Emerging Topics in Computational Intelligence, April 2026.<\/a><\/p>\n

Abstract<\/strong>: Leveraging their inherent suitability for low power, parallel computation, Spiking Neural Networks (SNNs) are an emergent topic in energy-efficient image processing research. This paper investigates the use of SNNs for line detection using an algorithm inspired by the Hough Transform. The implementation targets a Zynq UltraScale+ MPSoC ZCU102 FPGA to compare utilization, power, latency, and accuracy results with CNN, CPU, and GPU implementations. Our approach of using a neural network replicates the voting scheme found in the conventional Hough Transform, but is 2.2 times faster and requires up to 86% less accumulator-equivalent memory compared to recently published, competing FPGA implementations. Furthermore, it uses up to 97% (86%) less estimated power than equivalent OpenCV implementations running on a CPU (GPU), albeit with diminished accuracy. To ensure scalability, we employ kernel transformation techniques, in which a single hardware kernel is used to scan the entirety of the input image. As a result, hardware utilization is independent of image size up to the configured maximum resolution. The reported design is capable of processing a 100 by 100 pixel image in 13 microseconds, while requiring only 6.7 KiB of on-chip algorithm state (accumulators, line-parameter lookup tables, and weights) for line clustering. This implementation demonstrates the potential of SNNs for use in efficient, hardware-accelerated image processing tasks.<\/p>\n","protected":false},"excerpt":{"rendered":"

Aaron Yu; Arash Ahmadi; Leonard MacEachern, “A Spiking Neural Network Based Hough Transform Implementation for FPGAs”, IEEE Transactions on Emerging Topics in Computational Intelligence, April 2026. Abstract: Leveraging their inherent suitability for low power, parallel computation, Spiking Neural Networks (SNNs) are an emergent topic in energy-efficient image processing research. This paper investigates the use of […]<\/p>\n","protected":false},"author":5,"featured_media":0,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"_relevanssi_hide_post":"","_relevanssi_hide_content":"","_relevanssi_pin_for_all":"","_relevanssi_pin_keywords":"","_relevanssi_unpin_keywords":"","_relevanssi_related_keywords":"","_relevanssi_related_include_ids":"","_relevanssi_related_exclude_ids":"","_relevanssi_related_no_append":"","_relevanssi_related_not_related":"","_relevanssi_related_posts":"","_relevanssi_noindex_reason":"","_mi_skip_tracking":false,"_exactmetrics_sitenote_active":false,"_exactmetrics_sitenote_note":"","_exactmetrics_sitenote_category":0,"footnotes":"","_links_to":"","_links_to_target":""},"categories":[1],"tags":[],"yoast_head":"\nNew Publication - Specific-domain Hardware Research Laboratory<\/title>\n<meta name=\"description\" content=\"Aaron Yu; Arash Ahmadi; Leonard MacEachern, "A Spiking Neural Network Based Hough Transform Implementation for FPGAs", IEEE Transactions on Emerging\" \/>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"https:\/\/carleton.ca\/share\/2026\/new-publication-4\/\" \/>\n<meta name=\"twitter:label1\" content=\"Written by\" \/>\n\t<meta name=\"twitter:data1\" content=\"Arash Ahmadi\" \/>\n\t<meta name=\"twitter:label2\" content=\"Est. reading time\" \/>\n\t<meta name=\"twitter:data2\" content=\"2 minutes\" \/>\n<script type=\"application\/ld+json\" class=\"yoast-schema-graph\">{\"@context\":\"https:\/\/schema.org\",\"@graph\":[{\"@type\":\"WebPage\",\"@id\":\"https:\/\/carleton.ca\/share\/2026\/new-publication-4\/\",\"url\":\"https:\/\/carleton.ca\/share\/2026\/new-publication-4\/\",\"name\":\"New Publication - Specific-domain Hardware Research Laboratory\",\"isPartOf\":{\"@id\":\"https:\/\/carleton.ca\/share\/#website\"},\"datePublished\":\"2026-04-30T15:07:42+00:00\",\"dateModified\":\"2026-04-30T15:07:42+00:00\",\"author\":{\"@id\":\"https:\/\/carleton.ca\/share\/#\/schema\/person\/6d2b896d4b1d31635f6ffb65989690e5\"},\"description\":\"Aaron Yu; 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