April 22, 2026 | 4:30 PM – 6:00 PM | Nicol Building, Room 5010 | Carleton University
It was a great pleasure to host Dessislav Valkov, a senior FPGA engineer at Fidus Systems, for our Winter 2026 industry engagement series.
Drawing from his extensive industry experience, Des delivered a technical and highly practical talk covering advanced FPGA design topics including FSM RTL design, simulation automation, Clock Domain Crossing (CDC), SystemRDL, and SoC project structure and scripting. The session struck an excellent balance between depth and accessibility, and students engaged enthusiastically throughout with thoughtful questions and discussion.
This was Des’s second appearance in the series — having also joined us for the opening drop-in session in February — and his return was a fitting way to bring the series full circle. We extend our sincere thanks to Dessislav Valkov and the entire Fidus Systems team for an outstanding series of engagements this winter. Five sessions, five engineers, and countless meaningful conversations — this collaboration has made a lasting impact on our students and our community.
We look forward to continuing and deepening this partnership in the terms ahead.