Friday, June 26, 2026 | 10:00 AM – 11:00 AM
The SHaRe Lab is pleased to host Aliza Ghani on the Universal Verification Methodology (UVM) and its application to Spiking Neural Network Design.
Aliza will introduce UVM (IEEE 1800.2) as a framework for verifying complex digital designs, walking through the verification challenges that motivate it, its component-based testbench architecture, and the constrained-random, coverage-driven approach that makes it the industry standard. She will then connect the methodology to neuromorphic hardware, showing how UVM maps naturally onto the layered structure of spiking neural networks (SNNs), with a worked example built around a Leaky Integrate-and-Fire (LIF) neuron testbench. The talk closes with a concrete SystemVerilog and UVM skeleton illustrating how each functional block of an SNN core can be verified independently.
The session is open to all lab members and the wider department. Graduate and undergraduate students with an interest in VLSI verification, FPGA design, and neuromorphic hardware are warmly encouraged to attend.
Speaker Bio
Aliza Ghani is an undergraduate Electrical Engineering student at NUST Islamabad. Her interests include hardware verification and digital design, with a focus on using UVM for functional verification, coverage analysis, and verification automation.