Aaron Yu
DATE: Monday, August 17, 2026, 11:00, Location: online (Zoom link)
THESIS (MASc.) TITLE: Hardware-Optimized Spiking Neural Networks for High-Speed Event-Based Optical Flow Estimation
Abstract: This thesis presents EmFlow, a hardware-oriented spiking neural network (SNN) for high-speed embedded event-based optical flow estimation. EmFlow uses sparse convolutional processing, delayed upscaling, 1-bit spike feature maps, and limited persistent membrane state to reduce memory and computation. It is evaluated on HFlow320, a synthetic event-based human-motion dataset developed for this work, as well as MVSEC evaluation sequences and the DSEC optical-flow benchmark. With the baseline 25 ms hardware-oriented input window, EmFlow achieves 2.39 px endpoint error (EPE) and 35.02◦ average angular error (AAE) on HFlow320, 1.77 px EPE and 28.01◦ AAE on MVSEC, and 9.43 px EPE and 28.13◦ AAE on DSEC. The design is implemented on an AMD Kria KV260 field-programmable gate array (FPGA) with a Prophesee GenX320 event camera. The EmFlow accelerator module uses 9.6k look-up tables (LUTs), 11.8k flip-flops (FFs), 16 digital signal processing (DSP) blocks, 20/1 block RAM (BRAM) 36K/18K tiles, and 12 UltraRAM (URAM) tiles while sustaining a 40 frames/s (FPS) displayed output rate in live demonstrations. Event-to-observed-flow response measurements range from approximately 1.7 to 7 ms, while final displayed flow frames are accumulated over five 5 ms event windows. During operation, the system consumes 3.7 to 4.0 W total measured system-on-module (SOM) power, corresponding to approximately 0.1 to 0.4 W above the loaded idle baseline.