Partial Symbol Detection Based Energy-Efficient Receiver for Short-Reach Optical Communications

This thesis presents an energy-efficient architecture for optical receivers, targeting silicon photonic solutions for next-generation data centers. It introduces a partial symbol detection, MSB-based equalization scheme that can significantly reduce hardware complexity for multilevel signaling.

The design detects MSB bits from the incoming signal and uses MSB decisions to mitigate ISI from MSB transitions. This transforms the PAM-4 eye into a partially ISI-removed PAM-2 eye, reducing the number of comparators needed for a 1-tap PAM-4 DFE implementation from 12 to 4.

Simulations show the equalizer can equalize up to 66% of ISI, enabling reliable operation at 112 Gb/s. The architecture, post-layout extracted and simulated in 12nm-FinFET technology consumes 108.84mW at 112Gb/s using PAM-4 modulation. The receiver features TIA and CTLE followed by 8-way time-interleaved signal processing unit that corrects pre and post-cursor ISI. The inverter-based TIA topology provides 70dB gain, 29.65GHz bandwidth, and 1.59μA input-referred noise.

This research is focused on designing and developing a novel Partial Symbol Detection (MSB-Only Detection) equalizer to enhance the efficiency of DFE-based equalization for PAM-4 signaling in optical communication systems. Additionally, it involved optimizing the electrical analog front-end, including the TIA and equalizer chain to demonstrate the efficacy of the proposed equalizer.