Photo of Ram Achar

Ram Achar


Phone:613-520-2600 x 5651
Office:3036 Minto Centre
Website:Visit Professor Achar Website


Signal and power integrity; circuit modeling, simulation and optimization; high-speed interconnects; parallel algorithms; model-reduction techniques; CAD for RF, MEMS, wireless and optoelectronic applications; EMC/EMI; mixed-signal analysis; nonlinear circuit analysis/modeling.


Modern CAD tools to accelerate high-speed electronic product design.


  • Distinguished Lecturer (DLP), Circuits and Systems Society (2011-2013)
  • Guest Editor of IEEE – CPMT Transactions (2011)
  • General Co-Chair for EPEPS-2010, Austin and EPEPS-2011, San Jose
  • Chair of Joint Chapters of Circuits and Systems Society (CAS) – Electronic Devices Society (EDS), Solid State Circuits Society (SSC) of IEEE Ottawa Section
  • Steering Committee Member of IEEE International Conference on Electrical Performance of Electronic Packages (EPEPS) IEEE International Conference on Electrical Design of Advanced Packages (EDAPS)
  • Technical Program Committee Member of IEEE International Conferences: EPEPS, EDAPS, SPI
  • Technical Committee Member of Electrical Design, Modeling & Simulation (TC-EDMS- TC-12)
  • Senior Member of IEEE; IEEE MTT, CAS, EDS, SSC and EMC societies