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Ram Achar

Professor

Prof. Achar’s Website

Research Focus

My research advances Electronic Design Automation (EDA) with emphasis on circuit simulation and optimization by integrating physics-based AI-driven models and quantum-inspired algorithms. Focus areas include emerging chiplet architectures, co-packaged optics (CPO), and multi-domain signal, power, and thermal integrity for energy-efficient VLSI systems.

Emerging & Advanced Frontiers

Signal, Power, Thermal Integrity & Physical Domains

Core EDA & Simulation Algorithms

Application Domains

High-Speed Heterogeneous Systems – Signal, Power and Thermal Integrity

Modern microelectronic systems face unprecedented challenges driven by higher density, lower power, sub-nanometer scaling, and ultra-high operating speeds. High-speed interconnect effects, such as delay, attenuation, reflection, and crosstalk, remain dominant bottlenecks limiting performance across all system hierarchies, including ICs, chiplets, advanced packages, and printed circuit boards. At sub-nanometer nodes, severe process variability, tight power-noise margins, and steep heat dissipation requirements directly threaten design yield and reliability. Consequently, traditional boundaries across electrical, thermal, optical, and mechanical domains are rapidly vanishing.

My research focuses on developing next-generation Computer-Aided Design (CAD) algorithms and methodologies to model, analyze, and optimize complex high-speed circuits and systems. To tackle these emerging challenges, our work integrates Artificial Intelligence (AI) and Quantum Computing techniques into conventional CAD frameworks, while expanding analysis capabilities to advanced paradigms like 3D Integrated Circuits (3D ICs) and Co-Packaged Optics (CPO) alongside traditional VLSI Circuits, packages, interconnects, and mixed-domain applications.

Interdisciplinary CAD Solutions

Addressing these challenges requires the seamless integration of chip-package-system architectures with heterogeneous modules, including MEMS, RF, Co-Packaged Optics (CPO), electromagnetic, and optoelectronic components. Conventional CAD tools struggle to scale with this multi-domain complexity. By bridging the domain boundaries and leveraging the emerging advanced AI and quantum-enabled solver algorithms across heterogeneous computing platforms spanning CPUs, multi-core clusters, GPUs, and quantum processors, our research targets development of fast, accurate, and repeatable modeling, simulation and optimization tools. These solutions eliminate costly design iterations, accelerate time-to-market, and ensure high-yield, robust electronic systems.

Awards and Professional Activities (Recent and Selected)

Recognizing the strategic importance of the research, it has been awarded by several leading organizations and microelectronic forums:

Serving as the member of the BoG of the Electromagnetic Compatibility Society.

Selected as the “Distinguished Lecturer”, under the DLP program by the Electronic Packaging Society (EPS) to advance the area of Advanced packaging, High-Speed Interconnects, Signal and Power Integrity.

Received the Best Conference Paper Award for the contribution, “Gauss-Newton Method for Performance Evaluation of Decoupling Capacitors on Resonant Parallel Plates”, Proc. 29th IEEE International Conference on Electrical Performance of Electronic Packaging and Systems, pp. 1-3, Oct. 2020, San Jose, CA. This work was selected as the best paper of the conference (co-author).

Serving as the chair of the Distinguished Lecturer Program of the IEEE Electromagnetic Compatibility Society (EMCS). The responsibility in this task includes, soliciting DL speaker nominations, selecting DL speakers, DL talk/travel approvals, administering the DL budget and related interactions with the EMCS chapter chairs worldwide (Since 2017).

Selected as the “Distinguished Lecturer”, under the DLP program by the Electron Devices Society (EDS) to advance the area of nanoscale devices and interconnects and high-speed issues.

Selected as the “Distinguished Lecturer”, under the DLP program by the Electromagnetic Compatibility Society (EMCS) for years 2011 & 2012 to advance the area of signal and power integrity.

Recognized with the “Fellow of Engineers Institute of Canada (EIC)”, the highest grade of EIC membership for “Contributions to High-Speed Interconnect Analysis” (2015).

Conferred with the “Bharat Gaurav Award” (India Honor Award) by the India International Friendship Society (IIFS), at the  “Global Friendship Day” in New Delhi, India, Jan 2014. The Award is conferred to those individuals who have made outstanding contributions in their specialized fields while also significantly contributing to enhance the relationships between India and their chosen country.

B. Nouri, M. Nakhla, and R. Achar, “Optimum Order Estimation for Reduced Macromodels based on a Geometrical Approach to Model Order Reduction,” IEEE Transactions on Components, Packaging and Manufacturing Technology, pp. 1218-1227, July 2013. This work was selected as the best contributions paper for the year 2013 by the editorial board of IEEE TCPMT (co-author).

Recognized with the “Fellow of IEEE”, the highest grade of IEEE membership for “Contributions to Interconnects and Signal Integrity Analysis in High-Speed Designs” (2013).

Guest Editor for two special issues of IEEE Transactions on Components, Packaging, Manufacturing and Technology (T-CPMT) on “Macromodeling and Variability in Nanoscale Designs” and “3D-ICs and Interconnects”.

Selected as the “Distinguished Lecturer”, under the DLP program by the Circuits and Systems Society (CASS) for years 2011 & 2012 to advance the area of signal and power integrity.

Founding Member and the General Chair for HPCPS (IEEE International Workshop on High-Performance Chip, Package and Systems: (www.hpcps.org).

Invited by the Ministry of Information Technology and Communications of Government of India (MCIT-DIT). As part of this invitation, he visited (Nov-Dec 2011) and delivered a series of guest lectures focused on VLSI Interconnects and signal integrity at several premier institutes in India, including IISC-Bangalore, IIT–Delhi, IIT-Bombay, IIT-Kharagpur, CEERI-Pilani and BITS-Pilani.

Chair of the joint chapter of Circuits and Systems Society (CAS), Electronics Devices Society (EDS) and Solid State Circuits Society (SSC) of Ottawa IEEE Section (Chair since 2005).

Elected as the General Co-Chair for the “IEEE International Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS)” for years 2010 (Austin, Texas) & 2011 (San Jose, California). EPEPS is the world’s premier conference focused on signal integrity, power integrity, advanced packaging methodologies and high-speed interconnects. Also served as the chair of the Executive Committee and Technical Program committee of EPEPS.

Received the Best Conference Paper Award for the contribution, “A Novel Algorithm for Optimum Order Estimation of Reduced Macromodel, 15th IEEE International Workshop on Signal Propagation on Interconnects., pp. IV.4.1-IV.4.2, May 2011, Naples, Italy. This work was selected as the best paper of the conference (co-author).

Recipient of the prestigious Research Achievement Award (RAA) by the Carleton University. Each year Carleton university recognizes five professors for the excellence in their research. Award consists of a certificate and a research grant of $15,000.

Natlaie Nakhla was awarded the prestigious NSERC doctoral medal for her doctoral work on massively coupled interconnect analysis. Only four such medals are given in a year throughout Canada, among all Canadian universities as well as among all disciplines for outstanding research contribution (graduate student).

A. Narayanan received the Best Student Paper Award for the paper, “Fast EMI Analysis of Massively Coupled Interconnects with Long Delay”, in the IEEE Asia Pacific International Symposium on Electromagnetic Compatibility, Beijing, China, April 2010 (graduate student).

N. Nakhla, was the recipient of the Senate medal given by the Carleton University for her Doctoral work on “Waveform Relaxation and Transverse Partitioning Algorithms for Simulation of Massively coupled Interconnects”. This medal is given in each convocation ceremony, only when merited, to a graduate student for outstanding research achievement at the doctoral/masters level (graduate student).

P. Triverio, S.  Grivet-Talocia, M. Nakhla, F. Canavero and R. Achar, “Stability, causality, and passivity in electrical interconnect models,” IEEE Transactions on Advanced Packaging (T-AdvP), pp. 795-808, Nov. 2007. This work was done in collaboration with Polytechnico di Torino and was selected as the best contributions paper for the year 2007 by IEEE T-AdvP (co-author).

N. Nakhla, was the recipient of the University medal given by the Carleton University for her Masters work on “Passive Macromodeling of Multiconductor Transmission Line Interconnects”. This medal is given in each convocation ceremony, only when merited, to a graduate student for outstanding research achievement at the doctoral/masters level (graduate student).

D. Paul, M. Nakhla, R. Achar and A. Weisshaar, “A Passive Algorithm for Modeling Frequency-Dependent Parameters of Coupled Interconnects”, IEEE 15th Topical Meeting on Electrical Performance of Electronic Packaging, pp. 185-188, Oct. 2006, Phoenix, AZ (graduate student).

D. Saraswat was the recipient of the Senate medal given by the Carleton University for his doctoral work, titled, “Global Compact Passive Macromodeling Algorithms for High-Speed Circuits”. This medal is given in each convocation ceremony, only when merited, to a graduate student for outstanding research achievement at the doctoral/masters level (graduate student).

N. Nakhla, was the recipient of the University medal given by the Carleton University for her Masters work on “Passive Macromodeling of Multiconductor Transmission Line Interconnects”. This medal is given in each convocation ceremony, only when merited, to a graduate student for outstanding research achievement at the doctoral/masters level (graduate student (graduate student).

D. Saraswat was the recipient of the Young Researcher of the Year – OCRI (Ottawa-Carleton Research Institute) Futures Award. This medal is awarded to the most promising student researcher of the National Capital Region, evaluated based on the research accomplishments and its impact (graduate student).

Recipient of the Research Achievement Award (RAA) by the Carleton University. Each year Carleton university recognizes few professors for their excellence in research. Award consists of a certificate and a research grant of $15,000.

N. Nakhla, A. Ruehli, M. Nakhla, and R. Achar, “Simulation of Coupled Interconnects using Waveform Relaxation and Transverse Partitioning”, IEEE 13th Topical Meeting on Electrical Performance of Electronic Packaging, pp. 25-28, Oct. 2004, Portland, Oregon, USA (graduate student).

A. Dounavis, N. Nakhla, R. Achar and M. Nakhla, “Delay Extraction and Passive Macromodeling of Lossy Coupled Transmission Lines“, IEEE 12th Topical Meeting on Electrical Performance of Electronic Packaging, pp. 295-298, New Jersey, Oct. 2003 (co-author).

D. Saraswat, R. Achar and M. Nakhla, “Passive Macromodels of Microwave Subnetworks Characterized by Measured/Simulated Data“, IEEE International Microwave Symposium, (IMS), pp. 999-1002, Philadelphia, USA, June 2003 (graduate student).

D. Saraswat was the recipient of the Senate medal given by the Carleton University for his Masters work, titled, “Passive Macromodeling of Subnetworks Characterized by Tabulated Data”. This medal is given in each convocation ceremony, only when merited, to a graduate student for outstanding research achievement at the doctoral/masters level (graduate student).

D. Saraswat, R. Achar and M. Nakhla, “A Fast Algorithm and Practical Considerations For Passive Macromodeling of Measured/Simulated Data”, IEEE 11th Topical Meeting on EPEP, Monterrey, CA, pp. 297-300, October 2002 (graduate student).

P. Gunupudi, R. Khazaka, A. Dounavis, R. Achar and M. Nakhla, “Global multi-level reduction technique for nonlinear simulation of high-speed interconnects“, Proc. IEEE Electrical Performance of Electronics Packaging, Boston, MA, Oct. 2001, pp. 259-262 (co-author).

Recipient of the prestigious NSERC doctoral medal for the doctoral work on high-speed interconnect analysis. Only four such medals are given in a year throughout Canada, among all Canadian universities as well as among all disciplines for outstanding research contribution.

Recipient of the prestigious University Medal given by the Carleton University for the Ph. D. work, titled, “Model-reduction techniques for high-speed interconnect analysis”. This medal is given in each convocation ceremony, only when merited, to a graduate student for outstanding research and academic achievement.

R. Achar and M. Nakhla “A new algorithm for efficient simulation of on-chip integrated components”, Micronet Annual Workshop on Circuits and Systems in Canada, Feb. 1998, Ottawa, Canada.

P. Gunupudi, M. Nakhla and R. Achar, “Efficient simulation of high speed distributed interconnects using Krylov-subspace techniques”, IEEE 7th Topical meeting on Electrical Performance of Electronic Packaging, NY, Oct. 1998, pp. 295-298 (co-author).

R. Achar and M. Nakhla “A novel method for efficient simulation of high-speed VLSI designs”, Symposium on R&D in Microelectronics in Canada, June 1997, Ottawa, Canada. This paper was judged as the best demonstrated research by the awards panel and was awarded the first ever Strategic Microelectronics Consortium (SMC) Industrial Collaboration Award.

R. Achar and M. Nakhla, “An efficient algorithm for addressing high-frequency effects in VLSI interconnects with full-wave models”, Symposium on R&D in Microelectronics in Canada, June 1996, (Ottawa, Canada). This presentation was judged as the best CAD (Computer-Aided Design) paper focused on microelectronics or microsystems in the symposium and was awarded the 1996 CMC International Travel Award.

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