Raven 386-25 PC

Raven 386-25 PC

[Vin179]

The Raven desktop computer was a Carleton University branded PC clone from the 1980’s to 2000’s. They offered quality components and similar specs comparable to the original IBM computers. Purchasing components and assembling the computers onsite was a cost effective way to deploy computers at the university. The Raven 80386DX had a Ctrl+Alt+Ins ROM monitor for diagnostics and 386-era troubleshooting and OS transitions from MS-DOS to Windows/386.

• Manufacturer: Assembled at Carleton University
• Type: Desktop computer
• Release Date: 1992
• Cost at release: ~$5,000 (adjusted for inflation)
• MIPS: ~7

Hardware Specifications

• CPU: Intel 80386DX at 20/25 MHz (configurable).​
• Memory: Standard 1-2 MB onboard DRAM (removable); maximum 20-32 MB via 8 sockets (2 banks of 4).​
• Cache: 32-64 KB secondary cache (e.g., proto-COAST module on some boards).​
• Expansion: Multiple ISA slots for peripherals; typical AT-compatible bus.​
• Storage: Supported 3.5″/5.25″ floppy drives and IDE/ATAPI hard drives (configuration-dependent).​
• Video/Ports: Integrated or VGA-compatible options; serial, parallel, and keyboard ports standard.​
• Power: Custom AT-style connector; full AT desktop form factor.​
• Weight: ~12-15 kg

Operating System & Programming Languages 

• Operating System: MS-DOS (versions like 3.3 to 6.22), Windows 386/3.1
• Supported Languages:
  • Compiled Languages: C/C++, Pascal, Fortran, COBOL, BASIC (e.g., Microsoft QuickBASIC, PowerBASIC), leveraging MS-DOS compilers and 386 optimizations.​
  • Interpreted Languages: GW-BASIC, batch scripting; later Python via ports or emulators.​
  • Assembly: 80386 assembly with tools like MASM or TASM for low-level development.

Notables

• The ‘Raven’ brand computer was a Carleton University branded computer. It was a PC clone assembled at the university and configured to faculty or staff requirements.
• First Intel x86 CPU with full 32-bit internal/external architecture (275,000 transistors, 1.5 µm process), enabling 4 GB physical/64 TB virtual addressing.​
• Introduced protected mode multitasking, paging MMU, and 3-stage pipeline for 7 MIPS at 25 MHz (vs. 4-5 MIPS at 20 MHz).​
• Supported on-chip debugging, coprocessor interface (i387), and pipelined bus at 25 MHz/5V

Donated by: Carleton University ITS (formerly CCS)